1. Field of Invention
The present invention relates to a flash memory cell structure. More particularly, the present invention relates to a split-gate flash memory cell that has a sharp corner between the floating gate and the control gate, and the sharp corner is formed outside the channel region.
2. Description of Related Art
A conventional flash memory is a type of electrical erasable programmable read-only memory (EEPROM), which in turn is a type of non-volatile memory. In general, an EEPROM cell comprises two gates. One of the gates known as a floating gate is fabricated from polysilicon and is used for charge storage. The second gate known as the control gate is used for the controlling the input and output of data. The above floating gate is located beneath the control gate, and is generally in a floating state because there is no connection with external circuits. The control gate is normally wired to the word line. One of the characteristics of flash memory is its capacity for block-by-block memory erase. Furthermore, the speed of memory erase is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. For most other EEPROM, memory erase can take up to several minutes due to its bit-by-bit operation. Articles concerning flash memory are numerous, and one of them, which produces an improved flash memory structure, is described in U.S. Pat. No. 5,045,488, for example.
FIG. 1 is a cross-sectional view showing the flash memory cell structure similar to that illustrated in FIG. 4-S-a of U.S. Pat. No. 5,045,488. As shown in FIG. 1, a first gate 11 and a second gate 12 is formed above a semiconductor substrate 10. The first and second gates, for example, are polysilicon layers. In between the first gate 11 and the second gate 12, there is an insulating layer 13. The first gate 11, the insulating layer 13 and the second gate 12 together constitute a stacked-gate structure 14. On each sides of the stacked-gate structure 14, there is an ion-doped region in the substrate 10, namely, a source region 15 and a drain region 16. The characteristic of this type of flash memory cell structure is the split-gate design for the stacked-gate 14. In other words, the first gate 11 and the second gate 12 are distributed horizontally along the top of the substrate 10. Only a certain central portions of the first gate 11 and the second gate 12 overlaps such that one is stacked on top of the other in a vertical direction. Furthermore, the first gate 11 has sharp corners 17 for providing a high electric field, which confers a fast erase capability to the flash memory.
However, the aforementioned sharp corners 17 are located within the channel region. When the flash memory cells are repeated used, after many cycles, electrons will be trapped in the oxide dielectric layer around the corner areas. The amount of trapped electrons there will depend on the number of repeated charge/discharge cycles. Since these trapped electrons are located between the first gate and the second gate, electrical conductivity of the device will be affected. For example, one of the effects is to increase the threshold voltage of the device, leading to a lowering of the channel current. Such drift in the electrical properties is damaging to the operation of the device.
In light of the foregoing, there is a need in the art to improve the flash memory cell structure.